Digital computers and the like often include a plurality of VLSI circuits which are interconnected for binary communications by single segment or multi-segment transmission lines (collectively referred to herein as "transmission lines," but see a copending and commonly assigned Bruce et al. United States patent application which was filed Mar. 6, 1990 under Ser. No. 07/490,113 on "A Multi-Segmented Bus and Method of Operation" for a description of a computer bus composed of segmented, balanced transmission lines). Drivers and receivers interface the VLSI components of such systems to the transmission lines. The transmission lines, in turn, conventionally are traces which are formed on a suitable substrate, such as a PCB (printer circuit board). For example, so-called microstrip traces and strip line traces can be employed to form transmission lines having characteristics impedances on the order of about 50.OMEGA.-70.OMEGA.. Moreover, in keeping with standard practices, such transmission lines may have their opposite ends terminated in their characteristic impedance. Thus, the output load on a driver for such a transmission line may be as low as 25.OMEGA.-35.OMEGA. or so (i.e., the effective resistance of the parallel resistive terminations for the transmission line).
The power P.sub.i, dissipated internally of the driver is given by: EQU P.sub.i =vi (1)
where:
v=the voltage dropped across the driver; and PA1 i=the current drawn by the driver PA1 v.sub.t =the voltage level to which the transmission line is terminated; and PA1 R.sub.L =the effective load impedance provided by the transmission line.
To a first approximation, a binary driver functions as an open (non-conductive) or closed (conductive switch), so equation (1) can be rewritten to describe the power the driver internally dissipates when it is driving a terminated transmission line as: ##EQU1## where: v.sub.i =the voltage dropped across the driver when it is conducting;
Thus, it will be evident that the power internally dissipated by the driver is proportional to the nominal voltage swing (v.sub.t -v.sub.i) of the binary signal it applies to the transmission line and to the nominal low voltage limit of that signal (i.e., the logical "0" level).
As is known, CMOS technology is attractive for fabricating VLSI circuits having relatively high gate densities, but the nominal 5 v rail-to-rail voltage swing (nominally, 0 v-5 v) of standard CMOS circuits tends to cause the output drivers for such circuits to dissipate excessive amounts of power internally whenever the drivers are working into low impedance loads, such as terminated transmission lines of the above-described type. In recognition of that, others have proposed voltage buffering drivers and voltage translating receivers for interfacing CMOS circuits to such transmission lines. More particularly, proposals have been made for carrying out the binary communications between such circuits at TTL (transistor-transistor logic) signal levels (nominally 0 v-3.5 v), at PECL (positive emitter coupled logic) signal levels (nominally, 3.2 v-4.2 v), and at BTL (backplane transistor logic) signal levels (nominally, 1.1 v-2.0 v). From a power dissipation point of view, PECL and BTL signaling are superior to TTL signaling. However, PECL and BTL signaling are relatively difficult to implement in CMOS (indeed, the known BTL implementations are BiCMOS specific). TTL signaling is somewhat easier to implement in CMOS, but it provides only a modest improvement over rail-to-rail CMOS signaling from a power dissipation standpoint.
It, therefore, will be apparent that there is an urgent need for relatively low power drivers and for compatible receivers which can be economically and reliably implemented in existing CMOS technology for interfacing VLSI CMOS circuits to relatively low impedance terminated transmission lines.